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Lecture Digital Logic & Design: Lesson 16
Lecture Digital Logic & Design: Lesson 16 provide students with knowledge about carry propagation delay between 4-bit ALU units; carry propagation delay eliminated by using group carry; parallel comparators; comparison of numbers by cascaded 4-bit comparator; implementation of 4-bit comparator by cascading two 2-bit comparators;...
20 p stu 22/08/2023 27 0
Lecture Digital Logic & Design: Lesson 23
Lecture Digital Logic & Design: Lesson 23 provide students with knowledge about sequential logic; latch applications; the output of a switch connected to logic high; truth-table of positive and negative edge triggered D flip-flops; timing diagram of a Negative Edge triggered S-R flip-flop;...
53 p stu 22/08/2023 30 0
Digital Logic & Design - Lec_24
Lecture Digital Logic & Design: Lesson 24 provide students with knowledge about sequential logic; D flip-flop applications: data storage (fig 1, 2), synchronizing asynchronous inputs (fig 3,4,5,6), parallel data transfer (fig 7); J-K flip-flop and J-K flip-flop applications;...
7 p stu 22/08/2023 22 0
Lecture Digital Logic & Design: Lesson 27
Lecture Digital Logic & Design: Lesson 27 provide students with knowledge about sequential logic; asynchronous counters: down counters (fig 1), down counter with truncated sequence (fig 2); synchronous counters: synchronous counter (fig 3), synchronous decade counter (tab 1 fig 6);...
5 p stu 22/08/2023 18 0
Lecture Digital Logic & Design: Lesson 18
Lecture Digital Logic & Design: Lesson 18 provide students with knowledge about combinational functional devices; MUX applications: 2-digit decimal display circuit (fig 5), common cathode/anode displays (fig 6), 2-digit mux based display circuit (fig 7);...
5 p stu 22/08/2023 33 0
Lecture Digital Logic & Design: Lesson 19
Lecture Digital Logic & Design: Lesson 19 provide students with knowledge about programmable logic devices; programmable OR/AND gate arrays (fig 3); programmed OR/AND gate arrays (fig 4); PLD types: PROM (fig 5), PLA (fig 6), PAL (fig 7), GAL (fig 8); PAL programmed for SOP (fig 9);...
7 p stu 22/08/2023 21 0
Lecture Digital Logic & Design: Lesson 17
Lecture Digital Logic & Design: Lesson 17 provide students with knowledge about combinational functional devices; cascading ALUs without G.Carry (fig 1); cascading ALUs with G.Carry (fig 2); 16-bit ALU circuit (fig 3); cascading of comparators (tab 1 fig 5); iterative comparator (fig 6); MSI comparator (fig 7);...
7 p stu 22/08/2023 22 0
Lecture Digital Logic & Design: Lesson 26
Lecture Digital Logic & Design: Lesson 26 provide students with knowledge about J-K flip-flop circuit with potential timing problem; timing diagram of J-K flip-flop circuit with potential timing problem; Flip-flop circuit with potential timing problem due to clock; timing diagram of J-K flip-flop circuit with clock skew;...
32 p stu 22/08/2023 27 0
Lecture Digital Logic & Design: Lesson 20
Lecture Digital Logic & Design: Lesson 20 provide students with knowledge about programmable logic devices; PLA: implementing constant 0s and 1s (fig 1), implementing odd-prime number (fig 2); GALs: generic array logic structure (fig 3, 4), output logic macro cells OLMCs (fig 5), GAL ID (fig 6), programming of GAL;...
7 p stu 22/08/2023 26 0
Lecture Digital Logic & Design: Lesson 21
Lecture Digital Logic & Design: Lesson 21 provide students with knowledge about programmable logic devices; GAL16V8: emulate PALs three modes, OLMC; GAL16V8: simple mode (3 options), complex mode (2 options), registered mode; ABEL: acronym advanced boolean expression language;...
8 p stu 22/08/2023 33 0
Lecture Digital Logic & Design: Lesson 25
Lecture Digital Logic & Design: Lesson 25 provide students with knowledge about J-K flip-flop with asynchronous preset and clear inputs; logic symbol of a J-K flip-flop with asynchronous inputs; truth table of J-K flip-flop with asynchronous inputs; timing diagram of a J-K flip-flop with preset and clear inputs;...
23 p stu 22/08/2023 27 0
Lecture Digital Logic & Design: Lesson 22
Lecture Digital Logic & Design: Lesson 22 provide students with knowledge about sequential logic; ABEL input file (tab 1 fig 1); implementation of MUX (fig 2); latches and flip-flops; latch applications; logic symbols (fig 5); timing diagrams (fig 6);...
7 p stu 22/08/2023 25 0
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